1. Field of the Invention
The present invention relates to computer monitor display, and more particularly, to a method for continuously displaying graphics or video data during a non-responding period of a central processing unit (CPU). Herein, the graphics or video data are stored in a system memory that can only be accessed via an embedded memory controller inside the processor.
2. Description of the Prior Art
Graphics-intensive applications for computers such as personal computers (PC's) are becoming increasingly more popular. Such applications include high-end computer-aided drafting (CAD) applications, a multimedia game, MPEG (Moving Picture Experts Group) video playback, video conferencing, or one of many other real-time video applications. As these applications become more complex, they require the computers on which they are run to render and execute graphics much more quickly. Furthermore, as the typical resolution of computer screens has increased from 640.times.480 pixels (horizontal.times.vertical) to 800.times.600, 1024.times.768, 1280.times.1024 and beyond, and increased color information per pixel from two bits to 24 bits to 32 bits and beyond, the processing demand placed on the computers for fast graphics execution has also grown.
The typical computer relies on a graphics processing unit or a standalone graphics card, GFX, (also known as a video card, graphic accelerator card, or a display adapter, among other terms) to assist it in the display of graphics data on a display device. A graphics card generally includes a specialized processor or processors that are tailor-made for graphics rendering, as well as an amount of memory, ranging from one, two, four, eight, sixteen megabytes and up, so that a complete screen of graphics information, known as a frame, can be stored by the graphics card. This memory is generally known as a frame buffer of the graphics card.
Now please refer to FIG. 1 for a discrete-type computer system 10, which comprises a central processing unit (CPU) 11, a system chipset (commonly referred to as the north bridge, NB) 12, a datapath chipset (commonly referred to as the south bridge, SB) 13, a system memory 14, a graphics card (GFX) 15, a frame buffer 16, a display device 17 (such as a cathode ray tube, CRT, or a flat-panel type) and a built-in memory controller 18 inside the north bridge 12. Graphics “cards”, the graphics processing unit, may also be integrated within a single chip or into a chipset (such as the north bridge) on a motherboard of a computer. Please refer to FIG. 2 of such an integrated-type computer system 20, which comprises a CPU 21, a north bridge (NB) 22, a south bridge (SB) 23, a system memory 24 and a display device 25. The north bridge 22 has a built-in memory controller 26 and an integrated graphics processing unit (GFX) 27.
Graphics information to be displayed on the display device, such as cathode ray tube (CRT) or liquid crystal display (LCD), is stored in the system memory in preparation to being transferred to a video memory of the first-in-first-out (FIFO) type. The display FIFO of a graphics card requests system memory access, and may be envisioned as a storage tank of water (data) draining at a uniform rate from the bottom, and only occasionally being refilled from the top. The graphics card of the discrete-type computer system (shown in FIG. 1) or the graphics processing unit of the integrated-type computer system (shown in FIG. 2) can request access to the system memory directly through the memory controller in the north bridge (NB). In other words, the system memory access is requested by the graphics processing unit (or the graphics card) without going through the CPU.
Nevertheless, the computer system architectures shown in FIGS. 1 and 2 are not the only two system architectures that are in use, there are a few others, two examples of such other computer system architectures are shown in FIGS. 3 and 4. The computer system architecture 30 of FIG. 3 is similar to the discrete-type computer system 10 of FIG. 1, comprising a CPU 31, a north bridge (NB) 32, a south bridge (SB) 33, a system memory 34, a graphics card (GFX) 35, a frame buffer 36 and a display device 37, but also a built-in memory controller 38 inside the CPU 31. The computer system architecture 40 of FIG. 4 is similar to the integrated-type computer system 20 of FIG. 2, comprising a CPU 41, a north bridge (NB) 42, a south bridge (SB) 43, a system memory 44, a display device 45 and an integrated graphics processing unit (GFX) 47 in the north bridge 42, but also a built-in memory controller 46 in the CPU 41. The main differences between the computer system architectures of FIGS. 3 and 4 and the computer system architectures of FIGS. 1 and 2 are the placements of the memory controller and the system memory. The memory controller is integrated into the CPU in the computer system architectures of FIGS. 3 and 4, wherein the system memory is coupled to the CPU via the built-in memory controller. That is, the system memory access requested by the graphics processing unit (or the graphics card) has to go through not only the north bridge but the CPU as well.
Increased processor performance has often meant increased power consumption and shorter battery life (for mobile processor-based notebooks or lap tops). Power saving technique is a solution available now in most of the computer systems. When a state where an application program waits for input and a state where there is no input from an input device are continued for a predetermined time period, the supply of a clock from a CPU and the supply of power is stopped. Moreover, some applications require less processing power than others, the power saving technique can control the level of processor performance, dynamically adjusting the operating frequency and voltage many times per second, according to the task on hand. As a result, the power consumption is reduced, to extend the operating time of the batteries or reduce the battery capacity.
Nevertheless, the power saving technique often requires a period of a few μsec up to tens of μsec to process, so as to reduce the operating frequency. During that period (power saving process period), the CPU is in a complete idle state waiting for the alternation of the operating frequency. The graphics processing unit (or the graphics card) in the computer system architectures of FIGS. 3 and 4, or any architecture having the system memory directly coupled to the CPU, will not be able to request for system memory access through the CPU during the power saving process period. That is, no data can be obtained by the graphics processing unit (or the graphics card) to be displayed on the display device during that period.